Posted by
Maoyuan on Wednesday, March 03, 2010 10:10:18 PM
A contact structure provides electrical contact between two
polycrystalline silicon
interconnect layers. The lower layer has a silicide layer on its upper
surface. The upper polycrystalline silicon layer can be doped with a
different conductivity type, and makes an ohmic contact with the
silicided region of the lower polycrystalline silicon layer.
Chemical vapor deposition (CVD) is a chemical process that uses a
chamber of reactive gas to synthesize high-purity, high-performance
solid materials, such as electronics components. Certain components of
integrated circuits require electronics made from the materials
polysilicon, silicon dioxide, and silicon nitride. An example of a
chemical vapor deposition process is the synthesis of polycrystalline
silicon from silane (SiH4), using this reaction:
In semiconductor circuits, it is known that ohmic contacts are
desirable between interconnect layers. An ohmic contact is one in which
no P-N junction is formed.
When
polycrystalline silicon
interconnect lines having different conductivity types make contact, a
P-N junction is formed. A similar junction can be formed when
polycrystalline silicon having the same conductivity type, but very
different doping levels (such as N - - to N + ) make contact. For
various reasons, it is often desirable to have interconnect having
different conductivity types make contact, and it would be desirable to
provide an ohmic contact for such structures.
It is therefore an object of the present invention to provide an ohmic
contact between polycrystalline silicon interconnect layers having
different conductivity types.
It is another object of the present invention to provide such a contact
which is easily formed with a process compatible with existing process
technologies.
It is a further object of the present invention to provide such a
contact which is suitable for use in an SRAM structure to provide a
load.
Therefore, according to the present invention, a contact structure provides electrical contact between two
polycrystalline silicons
interconnect layers. The lower layer has a silicide layer on its upper
surface. The upper polycrystalline silicon layer can be doped with a
different conductivity type, and makes an ohmic contact with the
silicided region of the lower polycrystalline silicon layer.
In the silane reaction, the medium would either be pure silane gas, or
silane with 70-80% nitrogen. Using a temperature between 600 and 650 °C
(1100 - 1200 °F), and pressure between 25 and 150 Pa — less than a
thousandth of an atmosphere — pure silicon can be deposited at a rate
of between 10 and 20 nm per minute, perfect for many circuit board
components, whose thickness is measured in microns. In general,
temperatures inside a chemical vapor temperature deposition machine are
high, while pressures are very low. The lowest pressures, under 10−6
pascals, are called ultrahigh vacuum. This is different than the use of
the term "ultrahigh vacuum" in other fields, where it usually refers to
a pressure below 10−7 pascals instead.
Some products of chemical vapor deposition include
polycrystalline silicon manufacturer
, carbon fiber, carbon nanofibers, filaments, carbon nanotubes, silicon
dioxide, silicon-germanium, tungsten, silicon carbide, silicon nitride,
silicon oxynitride, titanium nitride, and diamond. Mass-producing
materials using chemical vapor deposition can get very expensive due to
the power requirements of the process, which partially accounts for the
extremely high cost (hundreds of millions of dollars) of semiconductor
factories. Chemical vapor deposition reactions often leave byproducts,
which must be removed by a continuous gas flow.
The process steps and structures described below do not form a complete
process flow for manufacturing integrated circuits. The present
invention can be practiced in conjunction with integrated circuit
fabrication techniques currently used in the art, and only so much of
the commonly practiced process steps are included as are necessary for
an understanding of the present invention. The figures representing
cross-sections of portions of an integrated circuit during fabrication
are not drawn to scale, but instead are drawn so as to illustrate the
important features of the invention.
Referring to FIG. 1, a semiconductor substrate 10 is partially covered
with an oxide layer 12. The oxide layer 12 is not complete over the
entire surface of the substrate 10, but that portion of interest to the
present description has no openings to the substrate 10.
A
polycrystalline silicon
layer 14 lies on the oxide layer 12. In the illustrative embodiment,
layer 14 is doped N-type. The polycrystalline silicon layer 14 has been
silicided to form a silicide layer 16 thereon. The polycrystalline
silicon 14 and silicide layer 16 have been patterned in a previous
processing step as known in the art to form a signal line. The
polycrystalline silicon layer 14 may be a first polycrystalline silicon
layer, such as commonly used to form gate electrodes of field effect
devices. Alternatively, polycrystalline silicon layer 14 may be a
second or later level used for interconnect between different portions
of an integrated circuit device. At the processing stage shown in FIG.
1, the transistors of the device have already been formed.
Once the polycrystalline silicon and silicide layers 14, 16 have been
formed and patterned, an oxide layer 18 is formed over the surface of
the device. Oxide layer 18 is typically a thin oxide layer, having a
thickness of between 500 and 1000 angstroms. The thickness of oxide
layer 18 may be any thickness which is compatible with the fabrication
process with which the invention described herein is being used.
Referring to FIG. 2, oxide layer 18 is patterned and etched to define a
contact opening 20 to the upper surface of the silicide layer 16. A
layer of
polycrystalline silicon 22 is then deposited over the surface of the device.
A light dosage of boron is implanted into the polycrystalline silicon
layer 22 in order to convert it to a P-type conductor. A typical dosage
would be approximately 10 13 atoms/cm 2 .
Referring to FIG. 3, the polycrystalline silicon layer 22 is then
masked, and a heavy arsenic implant made to define an N + region 24. A
typical dosage for such implant is 5×10 15 atoms/cm 2 . Such doping
level is used to allow the N + region 24 to be used as a power supply
line.
A P-N junction 26 is formed at the interface between the N + region 24
and the lightly P-doped polycrystalline silicon layer 22. The doping of
polycrystalline silicon layer 22 is low enough to define a resistor,
but is sufficiently high to cause degeneration in the contact opening
20, providing an ohmic contact between the
polycrystalline silicon layer
22 and the silicide layer 16. Thus, although the polycrystalline
silicon layer 14 is N-type, no P-N junction is formed at the contact
between the two layers 14, 22.
After formation of the highly doped N + regions 24, the polycrystalline
silicon layer 22 is etched to define interconnect, leaving the
structure shown in FIG. 3. The device is then ready for formation of
further oxide and interconnect levels as desired.
Referring to FIG. 4, a 4-transistor SRAM cell is shown. The contact
structure formed in FIG. 1-3 is suitable for use as a load element in
the cell of FIG. 4.
Cross-coupled field effect devices 30, 32 form the basis of the SRAM
cell. Access transistors 34, 36 connect the bit line BL and
complemented bit line BL' to common nodes 38, 40, respectively. Access
transistors 34, 36 are driven by the word line 42 as known in the art.
Node 38 is connected to the power supply line V cc through resistor 44
and diode 46. Node 40 is connected to V cc through resistor 48 and
diode 50.
Node 38 corresponds to contact opening 20 in FIG. 3. Resistor 44 corresponds to
polycrystalline silicon
region 22 of FIG. 3, with diode 46 being formed at the junction 26.
Node 40, resistor 48, and diode 50 correspond to FIG. 3 in a similar
manner.
Since the contact at contact opening 20, corresponding to nodes 38 and
40, is an ohmic contact, the load for the SRAM cell is formed by a
resistor and a diode rather than back-to-back polycrystalline silicon
diodes. In some SRAM cell designs, this can provide improved
performance over the use of a resistor alone, or back-to-back
polycrystalline silicon diodes.
A similar ohmic contact can be formed between a lower
polycrystalline silicon layer
which is doped P-type and an upper N-type layer. The silicide layer
prevents formation of a P-N junction in the contact opening.
While the invention has been particularly shown and described with
reference to a preferred embodiment, it will be understood by those
skilled in the art that various changes in form and detail may be made
therein without departing from the spirit and scope of the invention.